Field of Invention
The present invention relates to a high voltage metal oxide semiconductor (HVMOS) device; particularly, it relates to an N-type HVMOS device with enhanced breakdown voltage, and a P-type HVMOS device with reduced ON resistance, by defining a P-type dopant region. The present invention also relates to a method for making a HVMOS device.
Description of Related Art
The breakdown voltage between a source and a drain of a metal oxide semiconductor device is dependant on the PN junction between the source and the drain. As an example, an avalanche breakdown occurs when the electric field in the depletion region of the PN junction is high. The breakdown voltage limits the voltage applicable to the source and drain. If the breakdown happens at the PN junction between the source and drain, the current between the source and drain will be dramatically increased, damaging the PN junction and causing failure of the MOS device.
FIG. 1 shows a conventional structure of an N-type HVMOS device, which comprises: a substrate 11, a P-type well 12a, an N-type drift region 14a, an N-type source 15a, an N-type drain 18a, an N-type lightly doped region 16a, a threshold voltage adjustment P-type dopant region 19a, and a gate structure 17. The N-type lightly doped region 16a and the N-type drift region 14a help to enhance the breakdown voltage of the N-type HVMOS device. Both regions are formed by doping lower concentration N-type impurities at the PN junctions between the heavily doped source 15a or the drain 18a and the P-type well 12a, for purpose of increasing the width of the depletion region of the PN junctions to enhance the breakdown voltage of the N-type HVMOS device.
However, as the technology trend requires even smaller device dimension and even higher voltage applied to a high-voltage device, the aforementioned prior art has encountered a bottleneck. In the aforementioned prior art, although the breakdown voltage is increased, the ON resistance, another critical parameter for the device operation, is sacrificed.
On the other hand, for a conventional P-type HVMOS device, the bottleneck problem is that if the ON resistance is reduced, the breakdown voltage is sacrificed.
In view of the foregoing, the present invention provides an N-type HVMOS device with an enhanced breakdown voltage without sacrificing the ON resistance, and a P-type HVMOS device with a reduced ON resistance without sacrificing the breakdown voltage; the present invention also provides a method for making such devices.